1. Field of the Invention
This invention relates to a battery protection circuit for preventing at least overcharging of a secondary battery and an electronic device having the battery protection circuit.
2. Description of the Related Art
Among electronic devices loaded with battery packs for power supply, also referred to as a battery package, and adapted for being fed from the battery pack with the power for driving the devices, there are, for example, a portable so-called note-book type personal computer, occasionally abbreviated to note-book personal computer, an information terminal, a video tape recorder, a sound recorder, and a portable telephone. Among non-portable type electronic devices of this type, there is, for example, an electric car having, for example, a motor for assisting the motive power.
The battery packs used in these electronic devices are frequently provided with secondary battery cells that can be charged/discharged repeatedly. As such secondary battery cells, so-called lithium ion secondary batteries, having a high volumetric energy density, are frequently used.
However, the lithium ion secondary batteries are narrow in tolerance values for over-charging or over-discharging. Thus, the battery packs are usually provided with a battery protection circuit for preventing over-charging or over-discharging of the lithium ion secondary batteries.
FIG. 1 shows an illustrative structure of a conventional battery protection circuit provided in a battery pack 200 having a lithium ion secondary battery cell 202.
Referring to FIG. 1, terminals 211, 212 are charging/discharging terminals of the battery pack, with the terminal 211 being a battery plus terminal and with the terminal 212 being a battery minus terminal (GND side terminal). The battery pack 200 furnishes the current via these plus terminal 211 and minus terminal 212 from the battery cell 202 to a main body portion of the electronic device, by way of charging. On the other hand, the battery pack 202 is charged by the charging current furnished from an external charger, not shown, via these plus terminal 211 and minus terminal 212.
A field effect transistor (FET) 206 and another field effect transistor (FET) 205 are connected in series between a plus terminal 211 of the battery pack 200 and the positive terminal of the battery cell 202. The FETs 206, 205 are provided as a charging on/off controlling switching device and as a discharging on/off controlling switching device, respectively. These FETs 205, 206 are provided with parasitic diodes.
A control IC circuit 203 has its terminal 235 fed with a voltage value of the plus terminal 211, while having its terminals 231 and 232 fed with the positive terminal side voltage value and with the negative terminal side voltage value of the battery cell 202, respectively. The control IC circuit 203 outputs a driving signal for the switching operation (on/off operation) of the FET 206 and a driving signal for the switching operation (on/off operation) of the FET 205 from its terminals 233, 234, respectively. That is, the control IC circuit 203 monitors a voltage value of the plus terminal 211 and the voltage values of the positive and negative terminal sides of the battery cell 202 to control the switching operation (on/off operation) of the FETs 205, 206.
Meanwhile, in the battery pack employing the FET for charging/discharging control, as shown in FIG. 1, the two FETs 205, 206 are provided for charging/discharging control, these FETs 205, 206 being connected in series between the plus terminal 211 and the positive terminal side of the battery cell 202, thus undesirably raising the internal resistance. Although there is such a battery protection circuit having FETs connected in parallel to realize a low internal resistance, the number of component parts is increased in this case to raise the cost.
There are occasions wherein it is necessary to provide a spare protection circuit in addition to the inherent protection circuit, that is two protection circuits, thus further increasing the number of components and increased cost.
If, with the use of a dual FET with the outer shape TSSOP and an N channel, with a drain-to-source withstand voltage of 20 V, a gate withstand voltage of 12 V and with an on-resistance of 35 m.OMEGA., with gate voltage being 2.5 V, two such parallel-connected FETs are used for charging/discharging, the element resistance is 70 m.OMEGA., that is the resistance per FET is 35 m.OMEGA.. On the other hand, if these FETs are connected in series with each other, the element resistance is 35 m.OMEGA., that is the resistance per FET is 17.5 m.OMEGA.. FIG. 1 shows an example of a P-channel FET, which has a higher internal resistance than the N-channel FET, so that it is more undesirable.